As chip capacity continues to significantly increase, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized chip that is designed for a particular application. Notably, an FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity of FPGAs. Importantly, FPGAs can be designed using a variety of architectures which can include user configurable input/output blocks (IOBs) and programmable/configurable logic blocks (PLBs/CLBs) having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or “plugin card.” Advancement of FPGA technology has led to the development of FPGA-based system-on-chip (SoC), including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, a SoC can include all required ancillary electronics. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. FPGA-based SoCs with embedded operating systems (OSs) have further enhanced their popularity and flexibility.
FPGA-based SoCS have resulted in the proliferation of numerous consumer devices such as wireless telephones, personal digital assistants (PDAs), and digital cameras. In order for device manufacturers to develop FPGA-based SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or IP cores. An electronic file containing component information can typically be used to represent the core. A device manufacturer will generally acquire rights for one or more IP cores that are integrated to fabricate the SoC.
Notwithstanding the advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. Although a vast proportion of cores lie in the public domain, a significantly greater proportion of cores are proprietary. In order to use proprietary cores, a vast quantity of time, effort and money can be spent negotiating licensing agreements. Even after the cores are licensed, great care must be taken to properly integrate the cores prior to fabrication of the FPGA-based SoCs. Integration of the cores can include simulating, modeling and debugging the integrated cores in an operating environment. These tasks can be extremely daunting and time consuming and expensive. For example, during simulation and modeling, it can take hours if not days to simulate a few milliseconds of real time operation.
Importantly, verifying logic externally by probing the external pins has become increasingly difficult, if not impossible in certain scenarios. For example, flip-chip and ball grid array (BGA) packaging do not have exposed leads that can be physically probed using external tools such as an oscilloscope. Using traditional methods, capturing traces on devices running at system speeds in excess of 200 MHz can be challenging. Furthermore, most circuit boards are small and have multiple layers of epoxy, with lines buried deep within the epoxy layers. These lines are inaccessible using an external tool. Notably, attaching headers to sockets or SoCs to aid in debugging can have adverse effects on system timing, especially in the case of a high-speed bus. Notably, attaching headers can consume valuable printed circuit board (PCB) real estate.
Boundary-scan has been used to solve physical access problems resulting from high-density assemblies and packaging technologies used in PCB design. Boundary-scan solves physical access problems by embedding test circuitry, such as test access ports (TAPs), at chip level to debug, verify and test PCB assemblies. The institute of electronic engineers (IEEE) joint test action group (JTAG) has defined a standard, JTAG TAP also known as IEEE 1149.1, that utilizes boundary-scan for debugging and verifying PCB assemblies, such as SoCs.
FGPAs and IP cores utilized for SOC applications typically employ boundary-scan techniques by integrating one or more test access ports (TAPs), which can be used to verify and debug FPGA and embedded IP core logic. Notwithstanding the advantages of boundary-scan offered by JTAG TAP, there are inherent problems with debugging an verifying PCB assemblies that utilize multiple IP cores. For example, when multiple IP controller cores are utilized, the design arrangement of the IP controller cores can result in problems accessing each individual controller signals. Notably, such design arrangements are generally inflexible because they are hardwired and as a result, are permanent and non-programmable. Importantly, because of the non-programmability of such designs, designers have no choice but to test a hard-wired connection and subsequently re-wire the IP cores if changes are necessary. This often consumes a significant amount of development time, which translates directly into increased development cost.
The IP cores used in an SoC may have TAP controllers built into them. An SoC will generally have a TAP controller of its own. It would be desirable to have multiple TAPs on an SoC connected together so that they may be accessed simultaneously for test, debug, and other purposes. One method of connecting the TAPs together is to connect their Instruction Registers (IRs) in series in accordance with the present invention. This effectively creates a single, longer, IR. On a PLD, the connections between various IP blocks may be made through programmable interconnections. These interconnections are made by programming SRAM cells or other means. The interconnections do not exist prior to programming or configuration of the PLD. This leads to the problem that the IR will have one length prior to programming the PLD and a longer length afterward. Since it is required by the IEEE 1149.1 standard that the length of the Instruction Register (IR) of a TAP controller be fixed, this presents a problem.
One method of fixing this problem in accordance with the present invention is to have a selectable length shift register in the PLD TAP controller that can be placed in series with the PLD IR prior to programming. A multiplexer or other logic can be used to select between the output of the selectable shift register and the output of the IP core's IR. This selection can be made by a programmable SRAM cell as previously mentioned.
Given these inflexibilities and other inherent drawbacks, there is a need for a method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC).